module _12bitBIN2BCDb_test;

  reg [11:0] Bin;
  wire [3:0] BCD2,BCD1,BCD0;

  _12bitBIN2BCDb dut (
    .Bin(Bin),
    .BCD1(BCD1),
    .BCD2(BCD2),
    .BCD0(BCD0)
  );

  initial begin
    
    Bin =0000_0000_0001;
    #20; // 等待10个单位时间
  
    Bin =0000_0000_0000;
    #20;
    Bin =0010_0011_0111;
    #20; // 等待10个单位时间
    
    Bin =0010_0001_0111;
    #20;
    Bin =0010_0000_0111;
    #10; // 等待10个单位时间
    
    Bin =0010_0100_0111;
    #10;
    $finish; // 终止仿真
  end

endmodule